Altera Quartus Ii Pin Assignment

  1. March 1st, 2010, 03:36 AM#1
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    Pin assignment in Quartus II

    Hi all,

    After my design is added to the project if I tried to assign the pins automatically using compile Design option or I/O assignment analysis option available under compile design tool is giving a critical warning stating that "No exact pin location assignment for 29 pins of 49 total pins". This is happening for all my designs. Only Data pins are getting allocated every time i tried.

    Although i can allocate them manually using pin planner, but I need the default or suggested pin allocations.

    Kindly help me
  2. March 1st, 2010, 03:43 AM#2
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    Re: Pin assignment in Quartus II

    Forgot to mention the tool used. Quartus II

  3. Re: Pin assignment in Quartus II

    Hi,

    it is not clear to me what you try to achieve ? Do you have a board with an FPGA and want to assign your design ports to certain FPGA pins ? Can you post your <>.qsf file ?

    Kind regards

    GPK
    Originally Posted by laxmanvv
    Forgot to mention the tool used. Quartus II
  4. March 2nd, 2010, 12:11 AM#4
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    Re: Pin assignment in Quartus II

    I believe if you want to let Quartus II do the pin assignments for you, you don't have to go to pin assignment. Just compile the project and finish routing. It should be able to assign the pins for you randomly.
  5. March 2nd, 2010, 01:36 AM#5
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    Re: Pin assignment in Quartus II

    No its not allocating the pins even I just compiled the design. Just beacause it is not allocating I choose pin planner. I want the allocation without pin planner involvement.

  6. Re: Pin assignment in Quartus II

    You can allocate the pins in the HDL

    in SystemVerilog do:
    module a(
    (* chip_pin = "A13" *) input wire LVDS_RX,
    (* chip_pin = "A14" *) output reg LVDS_TX);
  7. March 2nd, 2010, 05:00 PM#7
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    Re: Pin assignment in Quartus II

    Last edited by kito; March 2nd, 2010 at 05:19 PM.
    Laxmanv. I assume you want to compile your design and stop quartus from warning about assigned pin locations? Is this what your asking?

    Normally if your using a dev kit, do not let quartus do pin assigment. However if your on a new design, then just compile it and quartus fitter will assign pins. Then use back annote assignments command.
  8. March 2nd, 2010, 10:13 PM#8
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    Re: Pin assignment in Quartus II

    Yeah, what you need to do is let Quartus II handle the random pin assignments. I believe it is the same for Xilinx ISE. Then after that, go to pin output file (in txt format) to view the pin report that is assigned by Quartus II
  9. March 3rd, 2010, 10:44 PM#9
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    Re: Pin assignment in Quartus II

    But I want the allocations in QSF. Lets take an example of Xilinx MIG. If we select any banks for user allocation then the pins get allocated in the selected banks by following pin allocation rules. If we didn't select any banks it 'll proceed with Default bank selections and outputs the UCF(user copnstraints file) with all pin alloctaions. I want the similar way here.
    Is there any option like that in IPtool bench or Quartus II?.

  10. Re: Pin assignment in Quartus II

    Hi,

    looks like that my post is missing.

    you can preserve the pin assignment choosen by Quartus. You have to back-annotade the assignment. You can do that in following way:

    Choose:

    Assignment -> Back-Annotate Assignments

    Stay with the default setting "Pin&device Assignment" and press ok.

    The assignments are now written into the QSF.

    Kind regards

    GPK
    Originally Posted by laxmanvv
    But I want the allocations in QSF. Lets take an example of Xilinx MIG. If we select any banks for user allocation then the pins get allocated in the selected banks by following pin allocation rules. If we didn't select any banks it 'll proceed with Default bank selections and outputs the UCF(user copnstraints file) with all pin alloctaions. I want the similar way here.
    Is there any option like that in IPtool bench or Quartus II?.

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  1. September 12th, 2011, 04:19 AM#1
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    how to auto-assign the pins

    I am using Quartus 2, I have a project that includes Cyclone 4. I have complicated deserialization and many LVDS pins. I want the tool to auto assign the pins. Even though the source code is ready with its top module and everything THE TOOL DOES NOT AUTO ASSIGN

    Somehow the tool does not auto-assign the pins.

    Can someone tell me clearly/step by step how to auto assign the pins of the FPGA using the Quartus.

    best regards
    Serkan

  2. Re: how to auto-assign the pins

    Err... what do you mean by auto-assign?
    The fitter will use an automatic assignmen to compile the design if you haven't yet done so.
    But to design the PCB, tou need to assign the pins manually.
  3. September 12th, 2011, 06:45 AM#3
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    Re: how to auto-assign the pins

    I have nothing to do with the PCB.
    The fitter does not automatically assigns pins.

    The tool does not assign pin locations to the signals on my top block/module.
    For instance if I have input signal `clock` on my top block and I compile it
    At the end of compilation when I open the pin planner I still see that the location and the I/0 bank of the signal is empty.

  4. Re: how to auto-assign the pins

    but why would you want it to assign signals to random pins?

    on a real PCB, signals will HAVE to be mapped to specific pins.
    If you have no pcb, and you're only concerned about build size, why do you care what pin the signal is connected to?

  5. Re: how to auto-assign the pins

    Hi Drogio,
    Maybe this is a stupid question...
    Did you connect your top level to I/O signals? If you simply instantiated the block but you don't connect its ports to outer world, no pin will be assigned.
  6. September 12th, 2011, 07:37 AM#6
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    Re: how to auto-assign the pins

    Of course of course.

    Maybe the tool cant do this because of the warning I got from the tool.
    Do you think the tool can not assign pins because it gives critical warning and cant find any pll for the required bank.

    ===============================================
    Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
    Critical Warning: No exact pin location assignment(s) for 153 pins of 153 total pins
    ...............................
    Info: Pin iTile4SerClk not assigned to an exact location on the device
    ...................................
    Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|main pll_altpll:auto_generated|pll1" in target device due to device constraints

  7. Re: how to auto-assign the pins

    If you dont assign pins it will pick random pins for your signals.
    I suggest you constrain all your pins. The FPGA is pretty useless without doing so.
  8. September 12th, 2011, 08:19 AM#8
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    Re: how to auto-assign the pins

    The thing is I could not make the tool pick random pins.

    Why I want to do that?
    Because there are 6 different data channels to be serialized and
    2 more clock inputs. I just need the basic information of tool assignments for clock inputs.

    Let me Re-fine my Question
    What can be done wrong so that the tool does not pick random pins(the design is synthesizing and working tested)
  9. September 12th, 2011, 08:37 AM#9
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    Re: how to auto-assign the pins

    To Tricky

    Sorry for the misunderstanding.
    I am doing this of course for the PCB.
    I am doing this because I am familiar with Xilinx and Spartan FPGAs. I am not familiar to
    Altera FPGA clocking structure
    Altera IO structure
    Since I have many peripherals I just wanted the know if the selected FPGA is ok to do the deserialization and serialization or in which bank

    I just wanted to see the automatically assigned clock inputs and outputs by PRESSING A BUTTON IN THE TOOL (like Xilinx) so that I will get some inspiration for my clocks (banks and pins)

  10. Re: how to auto-assign the pins

    PLLs on altera FPGAs usually have dedicated input pins. From the pin assignment, it works out which PLL to place into, rather than the other way round.

    Regardless, the clock pins will already be connected on the PCB, so you have to assign it mannually anyway (regardless of whether its Xilinx or Altera).

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